The lifetime, i.e. time between first use and failure, of semiconductor dies can be approximated by test structures. Electromigration (“EM”), i.e. the transport of atoms in metals due to the “electron wind” effect, can cause failure in semiconductor dies due to the formation of “voids,” i.e. open circuits, or “hillocks,” i.e. extrusions causing short circuits, in metals.
EM test structures simulate the failure of devices due to the effects of electromigration. The National Institute of Standards and Technology (“NIST”) has proposed a standard of 800.0 microns for EM test structure length. Conventional EM test structures-typically comprise a single metal line in a linear configuration having an EM test structure length of 800 microns. The single metal line is generally situated in a first metal layer of the conventional EM test structure, while test pads coupled to respective ends of the single metal line are typically situated in a second metal layer. An EM test can be performed by measuring a resistance of the single metal line. An EM failure can be determined when the measured resistance of the single metal line exceeds a predetermined resistance. However, conventional EM test structures capability of testing interlayer dielectric (“ILD”) reliability.
Thus, there exists a need in the art for a test structure to efficiently determine EM failure and ILD failure.